Referring initially to FIG. 1a, integrated circuits are formed on a semiconductor wafer 10 typically made from silicon. The wafer 10 is substantially round and typically has a diameter of approximately 15 to 20 cm. Each wafer 10 is divided up into individual circuit dies 15 which contain an integrated circuit. Since a single integrated circuit die 15 is often no more than 1 cm2, a great many integrated circuit dies 15 can be formed on a single wafer 10. After the wafer 10 has been processed to form a number of integrated circuit dies on its surface, the wafer 10 is cut along scribe lines 20 to separate the integrated circuit dies for subsequent packaging and use.
The structure of the dies (the wafer structure) is formed by a wafer manufacture process 21, which is generally outlined in FIG. 1b. In step 22, a mask or reticle design is made with the ultimate goal of attaining the desired wafer structure. The design is used in fabricating a mask or reticle in step 23. Finally, in step 24, the wafer is fabricated using a lithographic process such a photolithographic process is used to transfer the pattern of the mask or reticle to the wafer. In general, lithography refers to processes for pattern transfer between various media. The basic photolithography system consists of a light source, a photomask containing the pattern to be transferred to the wafer, a collection of lenses, and a means for aligning existing patterns on the wafer with patterns on the photomask. (The terms “mask” and “photomask,” as used herein, are intended to include both masks and reticles.)
Referring to FIG. 1c, during an intermediate stage in the manufacturing cycle, the wafer 10 is shown to include a film 25 which overlies the wafer 10 and a resist 30 deposited over the film 25. Exposing the resist 30 to light or radiation from a light source 32 of an appropriate wavelength, through a photomask 34, causes modifications in the molecular structure of the resist polymers to allow for transfer of the pattern from the photomask to the resist 30. The modification to the molecular structure allows a resist developer to dissolve and remove the resist in exposed areas, presuming a positive resist is used. If a negative resist is used, the developer removes the resist in the unexposed areas.
Referring to FIG. 1d, once the resist 30 on the wafer has been developed, one or more etching steps take place which ultimately allow for transferring the desired pattern to the wafer 10. For example, in order to etch the film 25 deposited between the resist 30 and the wafer 10, a wet or dry etchant is applied over the patterned resist 30. The etchant comes into contact with the underlying film layer by passing through openings 35 in the resist formed during the resist exposure and development steps. Thus, the etchant serves to etch away those regions of the film layer which correspond to the openings in the resist, thereby effectively transferring the pattern in the resist to the film layer as illustrated in FIG. 1e. In subsequent steps, the resist is removed and another etchant may be applied over the patterned film layer to transfer the pattern to the wafer or to another layer in a similar manner.
As performance demands in the semiconductor industry continue to increase, so does the device density of the patterns formed on the wafer. Accordingly, the line width, line space, and the size of contact holes (e.g. vias) have all significantly decreased such that controlling the critical dimensions (CDs) of features formed on a semiconductor wafer has become increasingly difficult. In order to maintain the integrity of the manufacture process it is very important to keep CD variations within a tolerable range. For this reason, various methods have been developed to measure CD variations in accordance with a selected figure of merit (FOM).
FOMs correspond to the criteria by which structures formed on the wafer are analyzed to determine how similar such structures are to the desired structure. Based on the outcome of such analysis, modifications in the mask design, the mask fabrication process, and/or the lithographic process, may be made in order to compensate for measured CD variations, thereby providing for more optimum chip design. For example, variations may be made to the lenses and/or mask patterns to account for measured CD variations.
One of the most common FOMs utilized today is a measurement of line width of a structure. For example, referring to FIG. 2, an image of a structure 50 is shown. The image of the structure 50 was obtained using a device such as a scanning electron microscope (SEM) which is known to provide high resolution images of structures formed on the wafer. As a basis for evaluating CD variations of the structure 50, a line width LW1 of the structure 50 is measured at a selected location approximately halfway between ends of the structure 50. The measured line width LW1 is then compared to a desired line width stored in memory to determine CD variations. Unfortunately, however, as can be seen from FIG. 2, the line width of the structure 50 may vary from one location to another. For example, the line width is narrower at some locations and wider at others. Accordingly, by measuring the line width of a structure at a selected location using SEM images, only a limited amount of information is obtained concerning the full extent of CD variations which may have occurred during the lithographic process.
Another method for determining the line width of a structure is known as the electrical line width measurement (ELM) technique. In accordance with ELM, the resistance of structures formed on the wafer is measured during application of a known amount of current. By comparing the resistance of a structure measured using ELM with an expected resistance of an optimally formed structure, an estimation of line width variation can be made. Unfortunately, while the information provided from implementation of the ELM technique is useful in monitoring CD variations, such information also fails to provide a full and accurate understanding of the precise nature of CD variations occurring in each structure. Various other CD variation calculation techniques are also known. However, it will be appreciated that depending on the FOM selected as a basis for CD analysis, an outcome of the analysis may provide incomplete and/or varying results.
Accordingly, there is a strong need in the art for a method and apparatus for quickly and easily analyzing the full extent of CD variations occurring across structures formed on semiconductor wafers.
Further, it is known that the pattern on the mask or reticle is always somewhat degraded compared with the designs generated by a designer. For example, some mask generation processes, such as use of laser pattern generators, tend to produce masks with rounded corners. Thus complex, sharply defined mask shapes produced by a designer, for example with features included for optical proximity correction (OPC), may not be accurately reproduced in mask designs. This suggests that mask designs with OPC require specialized mask generation processes, such as high-voltage e-beam pattern generation. However, use of such specialized processes may increase costs, and therefore in evaluating a mask generation process it would be desirable to evaluate the impact on the resulting wafer structure of the degradation of design due to mask formation.